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ASAHI KASEI
[AKD5381]
AKD5381
Evaluation board Rev.A for AK5381
GENERAL DESCRIPTION AKD5381 is an evaluation board for the digital audio 24bit 96kHz A/D converter, AK5381. The AKD5381 includes the input circuit and also has a digital interface transmitter. Further, the AKD5381 can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD5381 --Evaluation board for AK5381
FUNCTION * DIT with optical output * BNC connector for an external clock input
VA,VD
AGND,DGND
LIN
RIN
AK5381
AK4103 (DIT)
Opt Out
Clock Generator
DSP Data 10pin Header
Figure 1. AKD5381 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
-1-
2002/06
ASAHI KASEI
[AKD5381]
1. Evaluation Board Manual Operation sequence
1) Set up the power supply lines. [VA] (red) = 4.75 5.25V [VD] (orange) = 2.7 5.25V [VCC] (red) = 5V [AGND] (black) = 0V [DGND] (black) = 0V
: for VA of AK5381 (typ. 5.0V) : for VD of AK5381, 74LVC541 (typ. 5.0V) : for logic : for analog ground : for logic ground
Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5381 and AK4103 should be reset once bringing SW1 = "L" upon power-up.
Evaluation mode
(1) Slave Mode (1-1) A/D evaluation using DIT function of AK4103 PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the digitalamplifier which equips DIR input. Nothing should be connected to PORT2 (DSP). In case of using external clock through a BNC connector (J3), select EXT on JP10 (CLK) and short JP7 (XTE) and open JP12 (EXT).
JP3 SCLK JP5 LRCK JP7 XTE JP10 CLK JP12 EXT
XTL
EXT
(2) Master Mode (2-1) A/D evaluation using DIT function of AK4103 PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the digitalamplifier which equips DIR input. Nothing should be connected to PORT2 (DSP). In case of using external clock through a BNC connector (J3), select EXT on JP10 (CLK) and short JP7 (XTE) and open JP12 (EXT).
JP3 SCLK JP5 LRCK JP7 XTE JP10 CLK JP12 EXT
XTL
EXT
-2-
2002/06
ASAHI KASEI
[AKD5381]
Other jumper pins set up
1. JP1 (GND) : Analog ground and Digital ground OPEN : Separated. SHORT : Common. (The connector "DGND" can be open.) 2. JP2 (VA) : Select VA for AK5381 REG : Supply from regulator. VA connector should be supplied +15V. VA : Supply from VA connector 3. JP4 (REG) : Select VA for AK5381 OPEN : Not use regulator SHORT : Use regulator 4. JP6 (VD) : Select VD for AK5381 VA : Supply from VA connector VD : Supply from VD connector 5. JP8 (BCFS) : Select SCLK frequency 256 : In case of MCLK=256fs/512fs/768fs 384 : In case of MCLK=384fs 6. JP9 (MCLK) : Supply MCLK frequency for 74HC4040 256 : In case of MCLK=256fs 512 : In case of MCLK=512fs 768 : In case of MCLK=384fs/768fs 7. JP11 (LRFS) : Select LRCK frequency 256 : In case of MCLK=256fs/512fs/768fs 384 : In case of MCLK=384fs
-3-
2002/06
ASAHI KASEI
[AKD5381]
DIP Switch set up
[SW2] (MODE1): Setting the evaluation mode for AK5381 and AK4103 ON is "H", OFF is "L". No. 1 2 3 4 5 6 Name DIF CKS2 CKS1 CKS0 DIT1 DIT0 OFF ("L") MSB justified ON ("H") I2S Compatible
See Table 2 See Table 3 Table 1. Mode Setting
CKS2 L L L L H H H H
CKS1 L L H H L L H H
CKS0 L H L H L H L H
Input Level CMOS CMOS CMOS CMOS TTL
Master/Slave MCLK Slave 256/384/512/768fs Slave 256/384/512/768fs Master 256fs ( 96kHz) Master 512fs ( 48kHz) Slave 256/384/512/768fs Reserved CMOS ON Master 384fs ( 96kHz) CMOS ON Master 768fs ( 48kHz) Table 2. Mode Setting of AK5381
HPF ON OFF ON ON ON
SCLK 48fs or 32fs 48fs or 32fs 64fs 64fs 48fs or 32fs 64fs 64fs
Mode 0 1 2 3
DIT1 DIT0 MCLK fs OFF OFF 256fs 96kHz OFF ON N/A N/A ON OFF 512fs 48kHz ON ON 384fs 48kHz Table 3. MCLK Frequency Setting of AK4103
Default
Note: AK4103 does not support MCLK=768fs.
The function of the toggle SW
Upper-side is "H" and lower-side is "L". [SW1] (PDN): Resets the AK5381 and AK4103. Keep "H" during normal operation.
-4-
2002/06
ASAHI KASEI
[AKD5381]
Input Circuit
Analog signal is input to LIN/RIN pins via J1 and J2 connectors.
J1 RIN C1 10u AINR +
J2 LIN
C2 10u AINL +
Figure 2. LIN/RIN Input circuits
* AKM assumes no responsibility for the trouble when using the circuit examples.
-5-
2002/06
ASAHI KASEI
[AKD5381]
MEASUREMENT RESULTS
[Measurement condition] * Measurement unit * MCLK * SCLK * fs * Bit * Power Supply * Interface * Temperature
: Audio Precision, System Two Cascade : 256fs : 64fs : 48kHz, 96kHz : 24bit : VA = VD = 5.0V : DIT : Room
Parameter ADC Analog Input Characteristics: fs=48kHz S/(N+D) (-1dB Input) fs=96kHz fs=48kHz, A-weighted D-Range (-60dB Input) fs=96kHz S/N fs=48kHz, A-weighted fs=96kHz Interchannel Isolation
Result (Lch / Rch) 96.7 / 96.9 93.1 / 93.6 106.5 / 106.5 101.7 / 101.7 106.7 / 106.7 101.8 / 101.7 115.1 / 113.2
Unit dB dB dB dB dB dB dB
-6-
2002/06
ASAHI KASEI
[AKD5381]
[ADC Plot : fs=48kHz]
AKM AK5381 THD+N vs. Input Level VA=VD=5.0V, fs=48kHz, fin=1kHz
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B F S -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -120
-110
-100
-90
-80
-70
-60 dBr
-50
-40
-30
-20
-10
+0
Figure 1. THD+N vs. Input Level
AKM AK5381 THD+N vs. Input Frequency VA=VD=5.0V, fs=48kHz, Input=-1dBr
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B F S -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 2. THD+N vs. Input Frequency
-7-
2002/06
ASAHI KASEI
[AKD5381]
AKM
AK5381 Linearity VA=VD=5.0V, fs=48kHz, fin=1kHz
+0 -10 -20 -30 -40 -50
d B F S
-60 -70 -80 -90 -100 -110 -120 -120
-110
-100
-90
-80
-70
-60 dBr
-50
-40
-30
-20
-10
+0
Figure 3. Linearity
AKM AK5381 Frequency Response VA=VD=5.0V, fs=48kHz, Input=-1dBr
-0.5
-0.6
-0.7
-0.8
-0.9 d B F S
-1
-1.1
-1.2
-1.3
-1.4
-1.5 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 4. Frequency Response
-8-
2002/06
ASAHI KASEI
[AKD5381]
AKM
A K 5 3 8 1 C rosstalk VA=VD=5.0V, fs=48kHz, Input=-1dBr
-80 -85 -90 -95 -100 -105 -110
d B
-115 -120 -125 -130 -135 -140 -145 -150 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 5. Crosstalk
AKM AK5381 FFT Plot VA=VD=5.0V, fs=48kHz, Input=-1dBr, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 6. FFT Plot
-9-
2002/06
ASAHI KASEI
[AKD5381]
AKM
AK5381 FFT Plot VA=VD=5.0V, fs=48kHz, Input=-60dBr, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B F S
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 7. FFT Plot
AKM AK5381 FFT Plot VA=VD=5.0V, fs=48kHz, fin=None
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 8. FFT Plot
- 10 -
2002/06
ASAHI KASEI
[AKD5381]
[ADC Plot : fs=96kHz]
AKM AK5381 THD+N vs. Input Level VA=VD=5.0V, fs=96kHz, fin=1kHz
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B F S -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -120
-110
-100
-90
-80
-70
-60 dBr
-50
-40
-30
-20
-10
+0
Figure 9. THD+N vs. Input Level
AKM AK5381 THD+N vs. Input Frequency VA=VD=5.0V, fs=96kHz, Input=-1dBr
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B F S -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
40k
Figure 10. THD+N vs. Input Frequency
- 11 -
2002/06
ASAHI KASEI
[AKD5381]
AKM
AK5381 Linearity VA=VD=5.0V, fs=96kHz, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
d B F S
-130
-120
-110
-100
-90
-80
-70 dBr
-60
-50
-40
-30
-20
-10
+0
Figure 11. Linearity
AKM AK5381 Frequency Response VA=VD=5.0V, fs=96kHz, Input=-1dBr
-0.5
-0.6
-0.7
-0.8
-0.9 d B F S
-1
-1.1
-1.2
-1.3
-1.4
-1.5 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
40k
Figure 12. Frequency Response
- 12 -
2002/06
ASAHI KASEI
[AKD5381]
AKM
A K 5 3 8 1 C rosstalk VA=VD=5.0V, fs=96kHz, Input=-1dBr
-80 -85 -90 -95 -100 -105 -110
d B
-115 -120 -125 -130 -135 -140 -145 -150 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
40k
Figure 13. Crosstalk
AKM AK5381 FFT Plot VA=VD=5.0V, fs=96kHz, Input=-1dBr, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
Figure 14. FFT Plot
- 13 -
2002/06
ASAHI KASEI
[AKD5381]
AKM
AK5381 FFT Plot VA=VD=5.0V, fs=96kHz, Input=-60dBr, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B F S
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
Figure 15. FFT Plot
AKM AK5381 FFT Plot VA=VD=5.0V, fs=96kHz, fin=None
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
Figure 16. FFT Plot
- 14 -
2002/06
ASAHI KASEI
[AKD5381]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
- 15 -
2002/06
A
B
C
D
E
E
E
DGND
JP1 GND
AGND
J1 RIN
C1 10u +
D
D
J2 LIN
C2 10u + CKS1
CN1
U1
CN2
1
1
AINR
CKS0
16
16
CKS0
2
2
AINL
CKS2
15
15
CKS2
3
3
CKS1
DIF
14
14
DIF
VA VA
1
C
L1 (short)
2
JP4 REG
T1 TA48M05F
GND IN OUT
JP2 VA REG C6 0.1u R3 5.1
4
4
VCOM
PDN
13
13
5381_PDN R1 51 JP3 SCLK
5381_SSCLK
C3 2.2u
5
+ C4 0.1u
5 AGND SCLK 12 12
SCLK R2 51 5381_MCLK R4 51 5381_SLRCK JP5 LRCK LRCK
+ C9 47u
2
C5 0.1u
6
7
C10 10u VA
8
JP6 VD VD VD D3V
B
1 1
2
C12 47u
2
+
L2 (short)
A
A
B
+
C7 10u
C8 0.1u
6 VA MCLK 11 11
C
1
7
VD
LRCK
10
10
+ C11 0.1u
8 DGND SDTO 9 9
AK5381
SDTO
B
A
Title Size Document Number
AKD5381
AK5381
Sheet
E
Rev
A3
Date:
C D
A 1
of
Wednesday, March 27, 2002
3
A
B
C
D
E
VCC
E E
2
1
D1 HSU119
R5 10k U2A
1 2 3
U2B
4
PDN
L
3 1
H SW1 PDN
2
74HC14
74HC14 U3 VCC
1 V1 U1 24
C13 0.1u
D
D
2
TRANS
DIF2
23
VCC
3 RESETN DIF1 22
MCLK
4
MCLK
DIF0
21
DIF PORT1
4 3 2 1 5 6
5
SDTI
TXP
20
U4
VCC
6
BICK
TXN
19
C14 0.1u
R6 1k
IN VCC IF GND
5 6
DIT
1
C
G1
VCC
20
7
LRCK
DVSS
18
19
G2
GND
10
8
FS0/CSN
DVDD
17
SCLK
2
A1
Y1
18
9
FS1/CDTI
CKS1
16
DIT1
LRCK
3
A2
Y2
17
MCLK
16
SDTO
4
A3
Y3
MCLK SCLK LRCK SDTO
PORT2
1 2 3 4 5 10 9 8 7 6
10
FS2/CCLK
CKS0
15
DIT0
11
FS3/CDTO
BLS
14
DSP
5 A4 Y4 15 12 C1 ANS 13
6
B
A5
Y5
14
AK4103
7
A6
Y6
13
8
A7
Y7
12
9
A8
Y8
11
74ACT541
A
A
B
C
D
+
C15 0.1u
C16 0.1u
C17 10u
C
B
A
Title Size Document Number
AKD5381
DIT
Sheet
E
Rev
A3
Date:
A 2
of
Wednesday, March 27, 2002
3
A
B
C
D
E
X1 12.288MHz
E E
MCLK R7 1M U5A
1 2 3
VCC U5B
4 4
JP7 XTE
74HCU04 C18 (open) C19 (open)
74HCU04
XTL
2 D
U7A 74AC74
Q 5
JP10 CLK EXT
256 512 768
JP9
256fs 10
11
U6
CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
384 256
JP8 BCFS 64fs
3
CLK CL Q 6
PR
MCLK
384 256
JP11 LRFS fs
D
D
J3 EXT
1
74HC4040 R8 51 JP12 EXT VCC U8
3 4 5 6 7 10 2 9 1 A B C D ENP ENT CLK LOAD CLR QA QB QC QD RCO 14 13 12 11 15
D3V U9
1
G1
VCC
20
C20 0.1u
19 G2 GND 10
74AC163
C
2
A1
Y1
18
5381_SLRCK
C
VCC
6 5
U2C 74HC14
DIF CKS2 CKS1 CKS0 DIT1 DIT0
SW2
1 2 3 4 5 6 12 11 10 9 8 7
3
A2
Y2
17
5381_MCLK
4
A3
Y3
16
5381_SSCLK
VCC for 74HC14, 74HCU04, 74HC4040, 74AC74 74AC163 C21 47u + C22 0.1u C23 0.1u C24 0.1u C25 0.1u C26 0.1u RP1
5 4 3 2 1
MODE
PDN
5
A4
Y4
15
5381_PDN
6
A5
Y5
14
DIF
DIT1 DIT0
7
A6
Y6
13
CKS2
47k
8
B
A7
Y7
12
CKS1
B
U5C
8 9 5 6
9
A8
Y8
11
CKS0
U2D 74HC14
10 11 9
74HCU04 U5D
8
VCC 74LVC541
U5E
11 10
D CLK
PR
U2E 74HC14
12 13
74HCU04
12 11
10
U7B 74AC74
Q 9
U2F 74HC14
13
CL
74HCU04 U5F
12
Q
8
74HCU04
A A
13
Title Size Document Number
AKD5381
LOGIC
Sheet
E
Rev
A3
Date:
A B C D
A 3
of
Wednesday, March 27, 2002
3

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